Hierarchical Modeling for VLSI Circuit Testing

Hierarchical Modeling for VLSI Circuit Testing Login for the JSON version of this page.

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Title: Hierarchical Modeling for VLSI Circuit Testing
ISBN-10: 1-4613-1527-1
ISBN-13: 978-1-4613-1527-8
Author(s): Debashis Bhattacharya
Publisher: Springer US
Published: 1990
Format: [electronic resource] /
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Pages: 871
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Description

Metadata

EAN: 9781461315278
ASIN: 1461315271
Prefix: 978
Group: 1
Group Name: English language
Group Identifier: 978-1
Registrant: 4613
Publication: 1527
Check Digit: 8
Formatted: 978-1-4613-1527-8

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