ESD in Silicon Integrated Circuits

By E. Ajith Amerasekera, E. A. Amerasekera, Charvaka Duvvury

Modeling of electrical overstress in integrated circuits

By Carlos H. Diaz

System Level ESD Co Design

By Harald Gossner, Charvaka Duvvury

Modeling of Electrical Overstress in Integrated Circuits

By Carlos H. Diaz

Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downw...

Modeling of Electrical Overstress in Integrated Circuits

By Charvaka Duvvury, Sung Mo Steve Kang, Carlos H. Diaz

ESD in Silicon Integrated Circuits

By E. Ajith Amerasekera, Charvaka Duvvury

System Level ESD Co Design

By Harald Gossner, Charvaka Duvvury

System Level ESD Co Design

By Harald Gossner, Charvaka Duvvury

System Level ESD Co Design

By Harald Gossner, Charvaka Duvvury

Esd in Silicon Integrated Circuits

By E. A. Amerasekera, Charvaka Duvvury