Timing Analysis and Optimization of Sequential Circuits

By Naresh Maheshwari

Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum are...

Design Automation for Timing Driven Layout Synthesis

By Sachin S. Sapatnekar

The automation of layout synthesis design under stringent timing specifications is essential for state-of-the-art VLSI circuits and systems design. Especially, the timing-driven layout synthesis wi...

Design Automation for Timing Driven Layout Synthesis

By S. Sapatnekar, Sung Mo Steve Kang

Layout Optimization in VLSI Design

By S. Sapatnekar, Bing Lu, Ding Zhu Du

Layout Optimization in VLSI Design

By S. Sapatnekar, Bing Bing Lu, Ding Zhu Ding Zhu Du

Timing Analysis and Optimization of Sequential Circuits

By S. Sapatnekar, Naresh Maheshwari

Timing Analysis and Optimization of Sequential Circuits describes CAD algorithms for analyzing and optimizing the timing behavior of sequential circuits with special reference to performance parame...

Design Automation for Timing-Driven Layout Synthesis

By S. Sapatnekar, Sachin S. Sapatnekar, Sung Mo Steve Kang